1. Field of the Invention
This invention relates generally to automatic layout optimization tools for semiconductor integrated circuit designs. More particularly, it relates to a new physical design tool that is able to increase the spacing between metal wires in the layout effectively and efficiently without violating any design rules.
2. Description of the Related Art
The flow for designing an integrated circuit (IC) can be roughly divided into the logical design phase and the physical design phase. The logical design phase includes several design stages: from the design specification to architectural behavioral design stage, to the register transfer level (RTL) design stage, to the gate design stage, after which the logical IC design is ready for the physical design phase. The physical design phase includes floor planning, placement, and routing, which produces the physical IC design layout.
Today, state-of-the-art integrated circuits usually contain tens of millions of transistors and over a million of metal wires on a single chip. To achieve a dense design, automatic physical design tools use the minimum spacing rules and the minimum width wires. The minimum spacing is usually only 1/10 micron or less, which is about the same or smaller than the size of dust particles. Consequently, bridging fault is one of the most critical reliability problems responsible for the lower yield in the semiconductor manufacturing process.
Bridging fault happens when the adjacent metal wires are inadvertently and erroneously connected due to dust contamination during the manufacturing process. The entire design could be ruined by a single dust particle lying between two different metal wires. Since the possibility of the dust contamination usually decreases by cubic root as the size of dust increases, even a very small increment on wire-to-wire spacing can remarkably avoid the false connection by the dust. Wire spreading is one of the most effective solutions to reduce bridging fault, hence reduce yield loss.
In addition to reducing dust related yield loss, wire spreading offers many other benefits. One of them is that it reduces the dummy metal fill for layout density control. Uniformed layout metal density is an important requirement for yield in the modern IC manufacture process. Generally, the dummy metal fill is inserted to the low density area in the layout to achieve a similar density as in the high density area. The problem is, the more the amount of metal fill, the more the manufacture variation, the more the possible yield loss.
Wire spreading increases the spacing between wires that originally follow the minimum spacing and, at the same time, decreases the spacing between wires which have more than the minimum spacing. The overall effect to the layout is that the metal density in the high density area is decreased and the metal density in the low density area is increased. The total amount of required dummy metal fill is reduced, so is the related yield loss.
Another benefit is that wire spreading reduces crosstalk noise. By enlarging the spacing between timing critical nets, the design performance can be greatly improved. What is more, the total capacitance of the layout is reduced by wire spreading, so the overall power consumption is reduced, which is welcomed in any designs.
Since wire spreading inevitably changes the wire routing path, the problem remains in how to increase the wire-to-wire spacing without causing any design rule violations.
Due to the nature of routing, the layout routers have to use the minimum spacing rule between wire paths during the routing stage. To fix timing or signal integrity problems, as one of the post-routing optimization, the router could enlarge the spacing between specific net pairs. However, the routers cannot achieve wire spreading which increase the wire-to-wire spacing on any possible nets throughout the whole layout.
Existing wire spreading tools that increase the net-to-net spacing on a routed layout through some automatic layout tool are based on the traditional geometrical layout representation. Since in a geometrical layout the wire path of every net has the determined shape and position, those wire paths imposes geometrical constrains on any modification to the layout. Consequently, to avoid introducing design rule violations, these geometrical layout based wire spreading tools have a limited capability. They usually can only process designs with less than 100K cells and usually take tens of hours or even days to complete the process.
Considering that the minimum size of a routing layout is usually over 1000K cells and that the routing can typically be completed within a few hours, there is a clear need in the art for an automatic layout optimization solution that can provide better and faster wire spreading on the whole layout effectively and efficiently without violating any design rules. The present invention addresses this need.